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rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm revision history revision 0.0 (oct.13, 1999)
rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm pin names * these pins are not used in this module. ** these pins should be nc in the system which does not support spd. pin name function a0 ~ a1 2 address input (multiplexed) ba0 ~ ba1 select bank dq0 ~ dq63 data input/output cb0 ~ cb7 check bit (data-in/data-out) clk0 clock input cke0 clock enable input cs0 , cs2 chip select input ras row address strobe cas colume address strobe we write enable dqm0 ~ 7 dqm v dd power supply (3.3v) v ss ground *v ref power supply for reference rege register enable sda serial data i/o scl serial clock sa0 ~ 2 address in eeprom du don t use nc no connection wp write protection pin configurations (front side/back side) pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 front v ss dq0 dq1 dq2 dq3 v dd dq4 dq5 dq6 dq7 dq8 v ss dq9 dq10 dq11 dq12 dq13 v dd dq14 dq15 cb0 cb1 v ss nc nc v dd we dqm0 pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 front dqm1 cs0 du v ss a0 a2 a4 a6 a8 a10/ap ba1 v dd v dd clk0 v ss du cs2 dqm2 dqm3 du v dd nc nc cb2 cb3 v ss dq16 dq17 pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 front dq18 dq19 v dd dq20 nc *v ref *cke1 v ss dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 v dd dq28 dq29 dq30 dq31 v ss *clk2 nc wp **sda **scl v dd pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 back v ss dq32 dq33 dq34 dq35 v dd dq36 dq37 dq38 dq39 dq40 v ss dq41 dq42 dq43 dq44 dq45 v dd dq46 dq47 cb4 cb5 v ss nc nc v dd cas dqm4 pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 back dqm5 * cs1 ras v ss a1 a3 a5 a7 a9 ba0 a11 v dd *clk1 a12 v ss cke0 * cs3 dqm6 dqm7 *a13 v dd nc nc cb6 cb7 v ss dq48 dq49 pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 back dq50 dq51 v dd dq52 nc *v ref rege v ss dq53 dq54 dq55 v ss dq56 dq57 dq58 dq59 v dd dq60 dq61 dq62 dq63 v ss *clk3 nc **sa0 **sa1 **sa2 v dd the samsung m377s3253at3 is a 32 m bit x 72 synchronous dynamic ram high density memory module. the samsung m 377s3253at3 consists of nine cmos 32 mx8 bit synchro- nous drams in tsop-ii 400mil packages, two 18-bits drive ics for input control signal, one pll in 24-pin tssop package for clock and one 2k eeprom in 8-pin tssop package for serial presence detect on a 168pin glass-epoxy substrate. two 0.22uf and one 0.0022uf decoupling capacitors are mounted on the printed circuit board in parallel for each sdram. the m 377s3253at3 is a dual in-line memory module and is intented for mounting into 168-pin edge connector sockets. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high band- width, high performance memory system applications. general description m377s3253at3 sdram dimm (intel 1.2 ver base) 32mx72 sdram dimm with pll & register based on 32mx8, 4banks 8k ref., 3.3v synchronous drams with spd feature samsung electronics co., ltd. reserves the right to change products and specifications without notice. ? performance range ? burst mode operation ? auto & self refresh capability ( 8192 cycles/64ms) ? lvttl compatible inputs and outputs ? single 3.3v 0.3v power supply ? mrs cycle with address key programs latency (access from column address) burst length (1, 2, 4, 8 & full page) data scramble (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock ? serial presence detect with eeprom ? pcb : height (1,500mil) , double sided component part no. max freq. (speed) m377s3253at3-c1h 100mhz (10ns @ cl=2) m377s3253at3-c1l 100mhz (10ns @ cl=3)
rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm pin configuration description pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqm cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. cke should be enabled 1clk+tss prior to valid command. a0 ~ a1 2 address row/column addresses are multiplexed on the same pins. row address : ra0 ~ ra1 2 , column address : ca0 ~ ca 9 ba0 ~ ba1 bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas , we active. dqm0 ~ 7 data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active. (byte masking) rege register enable the device operates in the transparent mode when rege is low. when rege is high, the device operates in the registered mode. in registered mode, the address and con- trol inputs are latched if clk is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of clk. rege is tied to v dd through 10k ohm resistor on pcb. so if rege of module is floating, this module will be operated as reg- istered mode. dq0 ~ 63 data input/output data inputs/outputs are multiplexed on the same pins. cb0 ~ 7 check bit check bits for ecc. wp write protection wp pin is connected to v ss through 47k w resistor. when wp is "high", eeprom programming will be inhibited and the entire memory will be write-protected. v dd /v ss power supply/ground power and ground for the input buffers and the core logic.
rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm a0~a9 ras , cas , we dqm0,1,4,5 cs0 rege pclk2 b 0 a0~b 0 a9 bras , bcas , bwe bdqm0,1,4,5 bcs0 sn74alvc162835 a10~a12,ba0~1 cs2 cke0 dqm2,3,6,7 b 0 a10~b 0 a12,bba0~1 bcs2 bcke0 bdqm2,3,6,7 v dd 10k w oe le sn74alvc162835 oe le functional block diagram functional block diagram clk cs cke add,ctl dqm dq0~7 d0 pclk0 bcs0 bcke0 b 0 a0~b 0 a12,bba0~1, bras , bcas , bwe bdqm0 dq0~7 clk cs cke add,ctl dqm dq0~7 d1 dq8~15 clk cs cke add,ctl dqm dq0~7 d2 pclk1 bdqm1 cb0~7 clk cs cke add,ctl dqm dq0~7 d3 clk cs cke add,ctl dqm dq0~7 d5 clk cs cke add,ctl dqm dq0~7 d4 clk cs cke add,ctl dqm dq0~7 d6 clk cs cke add,ctl dqm dq0~7 d8 bdqm7 dq56~63 clk cs cke add,ctl dqm dq0~7 d7 10 w 10 w bcs2 bdqm2 dq16~23 pclk3 bdqm3 dq24~31 bdqm4 dq32~39 bdqm5 dq40~47 bdqm6 dq48~55 serial pd sda scl a1 a2 a0 sa1 sa2 sa0 cdc2509 2 g a g n d 1 g a v c l 1y0 1y1 1y2 1y3 1y4 2y0 2y1 2y2 clk v ss 10 w v dd clk0 fbou wp 47k w 12 pf 10 w 10 w 10 w 10 w 10 w 10 w 10 w notes : address/control signals are connected to d2 through 100 ohms resistor. * note 1. unused clock termination : 10 w and 12pf 2. the actual values of cb will depend upon the pll chosen. cb *2 pclk0 pclk1 pclk2 pclk3
rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm *1. register input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk ras cas we ras cas we cas latency(refer to *1) tsac trdl read row active command row active write command precharge command 1clk td tr td tr td, tr = delay of register (74alvc162835) notes : 1. in case of module timing, command cycles delayed 1clk with respect to external input timing at the address and input signal because of the buffering in register (74alvc162835). therefore, input/output signals of read/write function sho uld be issued 1clk earlier as compared to unbuffered dimms. 2. d in is to be issued 1clock after write command in external timing because d in is issued directly to module. : don t care standard timing diagram with pll & register (cl=2, bl=4) *2. register output *3. sdram reg control signal( ras , cas , we ) *1 *2 *3 d out =2clk+1clk trac(refer to *1) trac(refer to *2) cas latency(refer to *2) dq qa0 qa1 qa2 qa3 db0 db1 db2 db3 =2clk precharge command
rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 9 w short circuit current i os 50 ma permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : dc operating conditions and characteristics recommended operating conditions (voltage referenced to vss = 0v, t a = 0 to 70 c) parameter symbol min typ max unit note supply voltage v dd 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v ddq +0.3 v 1 input low voltage v il -0.3 0 0.8 v 2 output high voltage v oh 2.4 - - v i oh = -2ma output low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -10 - 10 ua 3 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. notes : capacitance (v dd = 3.3v, t a = 23 c, f = 1mhz, v ref =1.4v 200 mv) parameter symbol min max unit input capacitance (a 0 ~ a 1 2 ) input capacitance ( ras , cas , we ) input capacitance (cke0) input capacitance (clk0) input capacitance ( cs0 , cs2 ) input capacitance (dqm0 ~ dqm7) input capacitance (ba0 ~ ba1) data input/output capacitance (dq0 ~ dq63) data input/output capacitance (cb0 ~ cb7) c in1 c in2 c in3 c in4 c in5 c in6 c in7 c out c out1 - - - - - - - - - 12 12 12 12 12 12 12 12 12 pf pf pf pf pf pf pf pf pf
rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition version unit note -1h -1l operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i o = 0 ma 1,490 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 1 0 ns 368 ma 3 i cc2 ps cke & clk v il (max), t cc = 20 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 1 0 ns input signals are changed one time during 2 0ns 494 ma 3 i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 146 active standby current in power-down mode i cc3 p cke v il (max), t cc = 1 0 ns 404 ma 3 i cc3 ps cke & clk v il (max), t cc = 56 active standby current in non power-down mode i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 1 0 ns input signals are changed one time during 2 0ns 620 ma 3 i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 227 ma 3 operating current (burst mode) i cc4 i o = 0ma page burst 4 banks activated t ccd =2clk 1,535 ma 1 refresh current i cc5 t rc 3 t rc (min) 2,300 ma 2 self refresh current i cc6 cke 0.2v 395 ma 3 1. measured with outputs open. 2. refresh period is 64ms. 3. measured with 1 pll & 2 drive ics. 4. unless otherwise noted, input swing level is cmos(v ih /v il =v ddq /v ssq ) notes :
rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm 3.3v 1200 w 870 w output 50pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 1.4v 50 w output 50pf z0 = 50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit ac operating test conditions (v dd = 3.3v 0.3v , t a = 0 to 70 c) parameter value unit ac input levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 (ac operating conditions unless otherwise noted) parameter symbol version unit note -1h -1l row active to row active delay t rrd (min) 20 20 ns 1 ras to cas delay t rcd (min) 20 20 ns 1 row precharge time t rp (min) 20 20 ns 1 row active time t ras (min) 50 50 ns 1 t ras (max) 100 us row cycle time t rc (min) 70 70 ns 1 last data in to row precharge t rdl (min) 2 clk 2.5 last data in to active delay t dal (min) 2 clk + 20 ns - 5 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 operating ac parameter 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. 5. for -1h/1l, trdl=1clk and tdal=1clk+20ns is also supported . samsung recommends trdl=2clk and tdal=2clk + 20ns. notes :
rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. notes : refer to the individual componenet, not the whole module. parameter symbol -1h -1l unit note min max min max clk cycle time cas latency=3 t cc 10 1000 10 1000 ns 1 cas latency=2 10 12 clk to valid output delay cas latency=3 t sac 6 6 ns 1,2 cas latency=2 6 7 output data hold time cas latency=3 t oh 3 3 ns 1,2 cas latency=2 3 3 clk high pulse width t ch 3 3 ns 3 clk low pulse width t cl 3 3 ns 3 input setup time t ss 2 2 ns 3 input hold time t sh 1 1 ns 3 clk to output in low-z t slz 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 6 6 ns 1 cas latency=2 6 7 ac characteristics (ac operating conditions unless otherwise noted)
rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm notes : 1. op code : operand code a 0 ~ a 1 2 & ba 0 ~ ba 1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clock cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if both ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank b is selected. if both ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2) simplified truth table ( v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 11, a 12 a 9 ~ a 10 note register mode register set h x l l l l x op code 1,2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~ a 9 ) 4 auto precharge enable h 4,5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~ a 9 ) 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h
rev. 0.0 oct.1999 m377s3253at3 pc100 registered dimm package dimensions units : inches (millimeters) 0.250 (6.350 ) detail a 0.123 0.005 (3.125 0.125) 0.250 (6.350 ) detail b 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100) 0.079 0.004 (2.000 0.100) tolerances : 0 .005(.13) unless otherwise specified the used device is 32 mx8 sdram, tsop sdram part no. : k4s 560832a 5.250 5.014 r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0 . 1 1 8 ( 3 . 0 0 0 ) 0.350 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) 0 . 7 0 0 ( 1 7 . 7 8 0 ) .118dia 0.004 (3.000dia 0.100) (8.890) a c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100 ) 0.054 (1.372) (127.350) (133.350) 1 . 5 0 0 ( 3 8 . 1 ) 0.118 (3.000) b reg pll reg 0.150 max 0.050 0.0039 (1.270 0.10) 0 . 1 5 7 m i n ( 3 . 9 9 m i n ) (3.81 max) 0.050 0.039 0.002 0.008 0.006 (0.200 0.150) (1.000 0. 050) (1.270 ) 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) detail c

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